| 摘要 |
The present invention relates to an integrated circuit (semiconductor device) for which consolidation of a fine CMOS and a medium/high-voltage MOSFET is assumed to be carried out. A feature of the present invention is a small width (channel length) of a channel region CH. Specifically, when the width of the channel region planarly overlapped with a gate electrode is L and the thickness of the gate electrode is t, the channel region is formed to have the width of the channel region being larger than or equal to ⅕ times the thickness t of the gate electrode and smaller than or equal to the thickness t. Thus, the width L of the channel region can be reduced, and variations in the threshold voltage can be reduced.
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