发明名称 WIDE-RANGE CLOCK MULTIPLIER
摘要 A variable-frequency input clock signal and a reference clock signal are compared during a frequency-compare interval to generate a value that indicates a ratio of their frequencies. The frequency-ratio value is then applied to configure a wide-range frequency-locking oscillator for operation with a narrowed input frequency range. Because the narrowed input frequency range is targeted to the input clock frequency, the wide-range oscillator is able to rapidly lock to a frequency multiple of the input clock frequency. Because the frequency-compare interval is also brief, an extremely fast-locking, clock-multiplying operation may be effected over a relatively wide range of input clock frequencies
申请公布号 US2013002318(A1) 申请公布日期 2013.01.03
申请号 US201213535690 申请日期 2012.06.28
申请人 LU YUE;ZERBE JARED L. 发明人 LU YUE;ZERBE JARED L.
分类号 H03L7/06 主分类号 H03L7/06
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