| 摘要 |
A method of deriving register transfer level representation of a logic circuit performing a multiplication as the sum of addends operation with a desired rounding position. In this, an error requirement to meet for the design rounding precision is derived. For each of the constant correction truncation (CCT) and the variable correction truncation (VCT) implementations a number of columns to discard is derived and a constant to include in the sum addends is also derived which will comply with the error requirement. For a least mean square (LMS) implementation, a number of columns to discard is derived which will comply with the error requirement. After discarding the columns and including the constants as appropriate, an RTL representation of the sum of addends operation is derived for each of the CCT, VCT and LMS implementations and a logic circuit synthesized for each of these. The logic circuit which gives the best implementation is selected for manufacture. |
