Circuit and method for generating a clock signal

摘要

A circuit comprises a frequency divider configured to receive an oscillating signal generated by an oscillator and to divide the oscillating signal into a clock signal, wherein the division ratio of the frequency divider is set to a value equal to one of: the integer part of the resonant frequency of the oscillator and the integer part of the resonant frequency of the oscillator plus 1. The circuit further comprises a control element which switchable connects or disconnects a calibration element to alter the frequency of the oscillation signal input to the frequency divider based on a number of oscillations that have transpired in the oscillating signal.