| 摘要 |
Disclosed are a small-area 64-point fast fourier transform (FFT) processor and an FFT method. According to an embodiment of the present invention an FFT processor, which is an FFT processor of a decimation in frequency (DIF) type for an orthogonal frequency division multiplexing (OFDM) system, comprises at least three stages, and calculates a 64-point FFT using a radix-4² algorithm, wherein each of the stages comprises a butterfly comprising an addition block and/or multiplication block and a delay commutator; and performs butterfly calculations using CSD coefficients, defines common patterns for the CSD coefficients and shares same, and calculates twiddle factors using the defined CSD coefficients and performs common sub-expression sharing (CSS)-type butterfly calculations using adders and shifts. |
