发明名称 Systems and methods for logic verification
摘要 Methods and systems for simulating logic may translate logic design into executable code for a multi-processor based parallel logic simulation device. A system may implement one or more parallel execution methods, which may include IPMD, MPMD, and/or DDMT.
申请公布号 US8341568(B2) 申请公布日期 2012.12.25
申请号 US20100840543 申请日期 2010.07.21
申请人 CHEN FEI;GAO GUANG R.;ET INTERNATIONAL, INC. 发明人 CHEN FEI;GAO GUANG R.
分类号 G06F17/50;G06F9/455 主分类号 G06F17/50
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