发明名称 Systems and Methods for Retimed Virtual Data Processing
摘要 Various embodiments of the present invention provide systems and methods for data processing system. As one example, a data processing circuit is described that includes an analog to digital converter, an online timing loop, and an offline timing loop. The analog to digital converter receives an analog input and provides a first series of data samples Each bit of the first series of data samples corresponds to the analog input at a time controlled by an updated sampling clock. The online timing loop modifies the updated sampling clock based at least in part upon a processed version of the first series of data samples.
申请公布号 US2012324307(A1) 申请公布日期 2012.12.20
申请号 US201213570050 申请日期 2012.08.08
申请人 LIU JINFENG;SONG HONGWEI;LSI CORPORATION 发明人 LIU JINFENG;SONG HONGWEI
分类号 G06F1/08;G06F11/10 主分类号 G06F1/08
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