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发明名称
Clock-edge modulated serial link with DC-balance control
摘要
申请公布号
EP2501090(A3)
申请公布日期
2012.12.19
申请号
EP20120167375
申请日期
2006.10.18
申请人
SILICON IMAGE, INC.
发明人
KIM, GYUDONG;CHOE, WON JUN;KIM, JAEHA;LEE, BONG-JOON;KIM, MIN-KYU;JEONG, DEOG-KYOON
分类号
H04L25/49;H04L7/00
主分类号
H04L25/49
代理机构
代理人
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地址
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