发明名称 VECTOR CONFIGURATION SYSTEM, METHOD, DEVICE AND PROGRAM AND CRYPTOGRAPHIC SYSTEM
摘要 <P>PROBLEM TO BE SOLVED: To provide a technology of setting each dimensionality of an attribute vector and a predicate vector on predicate logic for the logical sum of t logical products of n attributes to t+1. <P>SOLUTION: The vector configuration system includes a common parameter generation device 1 which generates common parameters r<SB POS="POST">1</SB>,r<SB POS="POST">2</SB>,...r<SB POS="POST">n</SB>that are elements or integers of F<SB POS="POST">q</SB>when n is a positive integer and the F<SB POS="POST">q</SB>represents a finite field, an attribute vector generation device 2 which generates an attribute vector having X<SP POS="POST">t</SP>,X<SP POS="POST">t-1</SP>,...,X<SP POS="POST">1</SP>,X<SP POS="POST">0</SP>as elements when t is a positive integer, x<SB POS="POST">1</SB>,x<SB POS="POST">2</SB>,...,x<SB POS="POST">n</SB>of F<SB POS="POST">q</SB>and X=&Sigma;<SB POS="POST">i=1</SB><SP POS="POST">n</SP>r<SB POS="POST">i</SB>x<SB POS="POST">i</SB>, and a predicate vector generation device 3 which generates a predicate vector having s<SB POS="POST">0</SB>,s<SB POS="POST">1</SB>,...,s<SB POS="POST">t</SB>as elements when V<SB POS="POST">j,1</SB>,V<SB POS="POST">j,2</SB>,...,V<SB POS="POST">j,n</SB>of F<SB POS="POST">q</SB>, V<SB POS="POST">j</SB>=-&Sigma;<SB POS="POST">i=1</SB><SP POS="POST">n</SP>r<SB POS="POST">i</SB>v<SB POS="POST">j,i</SB>, s<SB POS="POST">0</SB>=1, and s<SB POS="POST">k</SB>represents a k-order basic symmetrical expression of V<SB POS="POST">j</SB>. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2012249215(A) 申请公布日期 2012.12.13
申请号 JP20110121300 申请日期 2011.05.31
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 YOSHIDA REISEI;KOBAYASHI TETSUTARO;TAKAHASHI KATSUMI
分类号 H04L9/08 主分类号 H04L9/08
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