发明名称 A/D conversion circuit, solid-state image sensor, and camera system
摘要 There are provided an A/D conversion circuit in which a counter is made to be capable of performing counting at both edges of a clock, up/down count values can be switched while the up/down count values are held, and the duty of the counting operation is difficult to be distorted even with the both-edge counting, a solid-state image sensor, and a camera system. An ADC 15A is configured as an integrating-type A/D conversion circuit using a comparator 151 and a counter 152. The counter 152 has a function of switching a count mode from an up count to a down count and from a down count to an up count while a value is held, a function of performing counting at both rising and falling edges of an input clock CK at a frequency two times as high as that of the input clock, and a function of latching the input clock CK in accordance with an output signal of the comparator 151 and setting non-inverted or inverted data of the latched data to be data of an LSB.
申请公布号 US8330635(B2) 申请公布日期 2012.12.11
申请号 US20080678807 申请日期 2008.09.25
申请人 HISAMATSU YASUAKI;SONY CORPORATION 发明人 HISAMATSU YASUAKI
分类号 H03M1/12;H03M1/56;H04N5/335;H04N5/374;H04N5/376;H04N5/378 主分类号 H03M1/12
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