| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a logic synthesizer and the like capable of surely preventing erroneous connection regarding FF in logic synthesis. <P>SOLUTION: A logic synthesizer 10 includes a design specification storage part 11 storing data 111 on IC design specification, a library part 12 storing data 121 on circuit elements constituting IC, and a logic synthesis part 13 for designing a netlist 131 on the basis of the data 111 on the design specification stored in the design specification storage part 11 and the data 121 on the circuit elements stored in the library part 12. The library part 12 stores data on FF 20 having a structure in which the same Q output terminal 23 is branched into a Q output terminal 231 for logical connection and a Q_C output terminal 232 for clock line. The logic synthesis part 13 uses the data on the FF 20 stored in the library part 12 when designing the netlist 131. <P>COPYRIGHT: (C)2013,JPO&INPIT |
