发明名称 PROCESSOR SAFETY TEST CONTROL SYSTEMS AND METHODS
摘要 First, second, and third processor modules selectively execute a test having N test states while an ignition system of the vehicle is off. N is an integer greater than one. The N test states each include: the first processor module setting a first output to a first predetermined value for one of the N test states; the second processor module setting a second output to a second predetermined value for the one of the N test states; the third processor module setting a third output to a third predetermined value for the one of the N test states; a predetermined expectation for the one of the N test states; and at least one of the first, second, and third processor modules indicating a fault when a fourth output is different than the predetermined expectation. A control module sets the fourth output based on the first, second, and third outputs.
申请公布号 US2012310467(A1) 申请公布日期 2012.12.06
申请号 US201113150646 申请日期 2011.06.01
申请人 FAUCETT JAMES MASON;COSTIN MARK H.;TARBY DAVID DEAN;DOWNS, JR. AUBREY WALTER;GM GLOBAL TECHNOLOGY OPERATIONS LLC 发明人 FAUCETT JAMES MASON;COSTIN MARK H.;TARBY DAVID DEAN;DOWNS, JR. AUBREY WALTER
分类号 G01M17/00 主分类号 G01M17/00
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