| 摘要 |
A semiconductor memory apparatus includes a memory device having a first plane and a second plane and a repair address latch unit configured to latch a plurality of repair addresses outputted from the memory device. The apparatus also includes an address comparison unit configured to compare the plurality of repair addresses stored in the repair address latch unit and a first plane address and a second plane address which are sequentially inputted. A repair processing unit is configured to selectively activate corresponding memory cell groups of the first plane and the second plane in conformity with the comparison result of the address comparison unit under the control of a first plane signal, a second plane signal and a start pulse signal. |
