发明名称 Apparatus and method for decision feedback equalization
摘要 Disclosed is an apparatus including an odd data receiving unit that receives an input signal, an even data receiving unit that also receives the input signal, and a pattern filter. The odd data receiving unit samples a half-rate DFE equalized signal with an odd data timing clock to output data decision data. The even data receiving unit samples the half-rate DFE equalized signal with an even data timing clock having the phase shifted by 180 degrees from the odd data timing clock to output data decision data. The pattern filter selects one of the edge decision data sampled at the odd edge timing and at the even edge timing in response to the value of a data pattern of three consecutive bits obtained from the data decision data sampled at the odd and even data timings.
申请公布号 US8325792(B2) 申请公布日期 2012.12.04
申请号 US20090404714 申请日期 2009.03.16
申请人 SUNAGA KAZUHISA;TAN KENZO;NEC CORPORATION;RENESAS ELECTRONICS CORPORATION 发明人 SUNAGA KAZUHISA;TAN KENZO
分类号 H03K7/00 主分类号 H03K7/00
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