| 摘要 |
<P>PROBLEM TO BE SOLVED: To perform a simple evaluation test of a semiconductor device. <P>SOLUTION: A semiconductor device 10 comprising first and second core chips CC0 and CC1, each of which generates internal signals MA, is based on a technical concept in which each of the first and second core chips CC0 and CC1 is provided with second and third nodes N<SB POS="POST">2</SB>and N<SB POS="POST">3</SB>that are spirally connected with each other via a through-electrode and the internal signals MA to be observed are output to the outside through the second and third nodes N<SB POS="POST">2</SB>and N<SB POS="POST">3</SB>. Those output internal signals MA are observed by using an external tester or the like; thereby allowing evaluation tests of core chips to be performed in parallel. <P>COPYRIGHT: (C)2013,JPO&INPIT |
