发明名称 ERROR CORRECTION IN A STACKED MEMORY
摘要 <p>Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a stack of memory dies with user data and/or first level error correction data stored in a stripe across the memory dies. One such stack can include a second level error correction vault, such as a parity vault, to store parity data corresponding to the user data and/or first level error correction data. Additional apparatus, systems, and methods are disclosed.</p>
申请公布号 EP2521972(A2) 申请公布日期 2012.11.14
申请号 EP20100841595 申请日期 2010.12.22
申请人 MICRON TECHNOLOGY, INC. 发明人 JEDDELOH, JOE M.
分类号 G06F11/16;G06F11/10;G11C29/42 主分类号 G06F11/16
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