发明名称 Content addressable memory
摘要 An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.
申请公布号 US8310852(B2) 申请公布日期 2012.11.13
申请号 US201213419217 申请日期 2012.03.13
申请人 WATANABE NAOYA;HAYASHI ISAMU;AMANO TERUHIKO;MORISHITA FUKASHI;YOSHINAGA KENJI;AKIYAMA MIHOKO;MIYAZAKI SHINYA;ISHIBASHI MASAKAZU;DOSAKA KATSUMI;RENESAS ELECTRONICS CORPORATION 发明人 WATANABE NAOYA;HAYASHI ISAMU;AMANO TERUHIKO;MORISHITA FUKASHI;YOSHINAGA KENJI;AKIYAMA MIHOKO;MIYAZAKI SHINYA;ISHIBASHI MASAKAZU;DOSAKA KATSUMI
分类号 G11C15/00;G11C7/06;G11C7/12;G11C7/14;G11C7/22;G11C15/04 主分类号 G11C15/00
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