DLL having a different training interval during a voltage change

摘要

A delay locked loop (DLL) having an accelerated training interval during a voltage change. An integrated circuit (IC) includes a master DLL configured to generate a clock signal based upon a reference clock signal. The master DLL may train to the reference clock signal in response to a control signal. The IC also includes a control unit that is coupled to the master DLL and may provide the control signal at a first interval in response to receiving an indication that a supply voltage is being changed, and provide the control signal at a second interval in the absence of the indication.