发明名称 |
Semiconductor memory device |
摘要 |
A sense amplifier circuit senses and amplifies a signal read from memory cells arranged at intersections of word-lines and bit-lines. A write circuit reads first data held in a first memory cell of the memory cells, and writes second data corresponding to the first data in a second memory cell different from the first memory cell. A data latch circuit holds data read from the first memory cell. A logic operation circuit performs a logic operation using data read from the second memory cell and data held in the data latch circuit as input values and outputs third data as an operation value. A write-back circuit writes the third data back to the first memory cell. |
申请公布号 |
US8310884(B2) |
申请公布日期 |
2012.11.13 |
申请号 |
US20100723922 |
申请日期 |
2010.03.15 |
申请人 |
IWAI TAKAYUKI;FUJII SHUSO;MIYANO SHINJI;KABUSHIKI KAISHA TOSHIBA |
发明人 |
IWAI TAKAYUKI;FUJII SHUSO;MIYANO SHINJI |
分类号 |
G11C7/22 |
主分类号 |
G11C7/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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