发明名称 CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
摘要 <P>PROBLEM TO BE SOLVED: To provide a chip package and its manufacturing method. <P>SOLUTION: An embodiment of the present invention provides a manufacturing method of a chip package including: a step of providing a semiconductor wafer having a plurality of device regions separated by a plurality of scribe lines; a step of bonding a package substrate to the semiconductor wafer and installing a spacer layer between the package substrate and the semiconductor wafer, in which the spacer layer defines a plurality of cavities respectively exposing the device regions and has a plurality of through-holes neighboring an outer edge of the semiconductor wafer; a step of filling an adhesive material in the through-holes, in which the spacer layer has viscosity and the material thereof is different from the adhesive material; and a step of dicing the semiconductor wafer, the package substrate, and the spacer layer along the scribe lines to form a plurality of chip packages separated from each other. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2012222366(A) 申请公布日期 2012.11.12
申请号 JP20120092264 申请日期 2012.04.13
申请人 XITEC INC 发明人 YEN YU-LIN;LIU GUO HUA;HUANG YU-LONG;LIU TSANGYU;HO YEN-SHIH
分类号 H01L23/12;H01L21/60 主分类号 H01L23/12
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