| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a data transfer system capable of transferring data to a peripheral circuit from a master device without deteriorating system performance. <P>SOLUTION: The data transfer system comprises: master devices M1-M3; a bus bridge 3 to which data D1-D3 outputted via a first bus 2 from the master devices are input and which outputs the data via a second bus 4; and a peripheral circuit 5 having write buffers WB1-WB3 which store the data D1-D3 outputted from the bus bridge 3 and registers R1-R3 which store the data D1-D3 outputted from the write buffers WB1-WB3. The bus bridge 3 and the write buffer operate at a first clock, the register operates at a second clock which is asynchronous with the first clock, and the write buffer and the register are synchronized, thereby transferring the data to the register from the write buffer. <P>COPYRIGHT: (C)2013,JPO&INPIT |
