| 摘要 |
A clock generation circuit includes a first divider, a loop unit that has a second divider and generates an output clock which is in phase synchronization with a reference clock of the first divider and has a frequency that is F times the reference clock, a clock switching unit that selects one input clock among a plurality of input clocks and supplies the selected input clock to the first divider, and a timing control unit. The timing control unit switches the clock selection command in accordance with switching of clock selection information, switches at least one of a setting of the number R of the input clocks and a setting of the number F of the output clocks, and starts both of a count operation by using the first divider and a count operation by using the second divider after switching of the setting. |
