发明名称 |
SRAM CELL PARAMETER OPTIMIZATION |
摘要 |
An integrated circuit having an SRAM cell includes a pair of cross-coupled inverters with first driver and load transistors connected to provide a first storage node and second driver and load transistors connected to provide a second storage node. The SRAM cell also includes first and second pass gate transistors controlled by at least one word line and respectively connected between a first bit line and the first storage node and a second bit line and the second storage node; wherein a first driver transistor threshold voltage is different than a second driver transistor threshold voltage and one of the first and second driver threshold voltages is different than a pass gate transistor threshold voltage. Alternately, a threshold voltage of the first and second driver transistors is different than a symmetrical pass gate transistor threshold voltage. Additionally, methods of manufacturing an integrated circuit having an SRAM cell are provided.
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申请公布号 |
US2012275207(A1) |
申请公布日期 |
2012.11.01 |
申请号 |
US201113097370 |
申请日期 |
2011.04.29 |
申请人 |
HOUSTON THEODORE W.;KOHLI PUNEET;CHATTERJEE AMITAVA;TEXAS INSTRUMENTS INCORPORATED |
发明人 |
HOUSTON THEODORE W.;KOHLI PUNEET;CHATTERJEE AMITAVA |
分类号 |
G11C11/412;H01L21/8244 |
主分类号 |
G11C11/412 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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