发明名称 SIGNAL DECODING CIRCUIT, LATENCY ADJUSTMENT CIRCUIT, MEMORY CONTROLLER, PROCESSOR, COMPUTER, SIGNAL DECODING METHOD, AND LATENCY ADJUSTMENT METHOD
摘要 <p>A signal restoration circuit includes storage (4) and a storage controller (6). The storage (4) is configured to store input signals by disposing the input signals in an input order and the input signals are readable from the storage in the disposed order. The storage controller (6) is configured to control delay time from an input of the input signal to an output in the storage (4) based on delay information of the input signal. When a delay amount of the input signal is large, the delay time is reduced, and when the delay amount of the input signal is small, the delay time is increased.</p>
申请公布号 EP2518630(A1) 申请公布日期 2012.10.31
申请号 EP20090852589 申请日期 2009.12.25
申请人 FUJITSU LIMITED 发明人 TOKUHIRO NORIYUKI;TAKAHASHI NORIYUKI;AISO SHINYA
分类号 H03K5/13 主分类号 H03K5/13
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