| 摘要 |
A demultiplexer drive circuit includes a first, a second, a third, a fourth, and a fifth switching devices. The first switching device is connected to the first and the second scan clock signals. The control terminal of the second switching device is connected to the first switching device, and the rest of its terminals are connected to the data line and a first pixel electrode. The control terminal of the third switching device is connected to the first switching device, and the rest of its terminals are connected to the data line and a second pixel electrode. The fourth switching device is connected to the first and the second scan clock signals and its control terminal is connected to the third switching device. The control terminal of the fifth switching device is connected to the fourth switching device, and the rest of its terminals are connected to the data line and a third pixel electrode. The first scan clock signal and the second scan clock signal have a substantially identical pulse width and a phase difference of substantially half of the pulse width. |
