发明名称 DELAY LOCKED LOOP
摘要 A delay locked loop includes a delay unit delaying an input clock to generate an output clock, a replica delay unit delaying the output clock to generate a feedback clock, a phase comparing unit outputting a phase signal having a first or second value according to whether the phase of the feedback clock leads the phase of the input clock, a filtering unit generates a filtering signal in response to the phase signal and updates the filtering signal when a difference of count numbers of the phase signal having the first value and the second value is substantially equal to a filtering depth, a locking unit generates a locking signal in response to the filtering signal, and a control unit adjusts a delay value in response to the filtering signal and maintains the delay value when the locking signal is activated.
申请公布号 US2012268180(A1) 申请公布日期 2012.10.25
申请号 US201113190841 申请日期 2011.07.26
申请人 JANG JAE-MIN;KIM YONG-JU;CHOI HAE-RANG 发明人 JANG JAE-MIN;KIM YONG-JU;CHOI HAE-RANG
分类号 H03L7/06 主分类号 H03L7/06
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