发明名称 |
EFFICIENT DATA PREFETCHING IN THE PRESENCE OF LOAD HITS |
摘要 |
A memory subsystem in a microprocessor includes a first-level cache, a second-level cache, and a prefetch cache configured to speculatively prefetch cache lines from a memory external to the microprocessor. The second-level cache and the prefetch cache are configured to allow the same cache line to be simultaneously present in both. If a request by the first-level cache for a cache line hits in both the second-level cache and in the prefetch cache, the prefetch cache invalidates its copy of the cache line and the second-level cache provides the cache line to the first-level cache.
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申请公布号 |
US2012272004(A1) |
申请公布日期 |
2012.10.25 |
申请号 |
US201213535188 |
申请日期 |
2012.06.27 |
申请人 |
GLOVER CLINTON THOMAS;EDDY COLIN;HOOKER RODNEY E.;LOPER ALBERT J.;VIA TECHNOLOGIES, INC. |
发明人 |
GLOVER CLINTON THOMAS;EDDY COLIN;HOOKER RODNEY E.;LOPER ALBERT J. |
分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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地址 |
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