发明名称 Arithmetic processing apparatus and method
摘要 An apparatus includes a TLB storing a part of a TSB area included in a memory accessed by the apparatus. The TSB area stores an address translation pair for translating a virtual address into a physical address. The apparatus further includes a cache memory that temporarily stores the pair; a storing unit that stores a starting physical address of the pair stored in the memory unit; a calculating unit that calculates, based on the starting physical address and a virtual address to be converted, a TSB pointer used in obtaining from the TSB area a corresponding address translation pair corresponding to the virtual address to be converted; and an obtaining unit that obtains the corresponding pair from the TSB area using the TSB pointer calculated and stores the corresponding pair in the cache memory, if the corresponding pair is not retrieved from the TLB or the cache memory.
申请公布号 US8296518(B2) 申请公布日期 2012.10.23
申请号 US20090624531 申请日期 2009.11.24
申请人 MARUYAMA MASAHARU;FUJITSU LIMITED 发明人 MARUYAMA MASAHARU
分类号 G06F12/08;G06F12/10 主分类号 G06F12/08
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