发明名称 |
Handling two-dimensional constraints in integrated circuit layout |
摘要 |
A computer-implemented method for handling a plurality of constraints in layout optimization for an integrated circuit (IC) layout is disclosed. In one embodiment, the method includes building a graph representing the plurality of constraints; marking two-dimensional constraints in the plurality of constraints; generating two-dimensional clusters including groups of the two-dimensional constraints; handling at least one of the two-dimensional clusters, the handling including finding a solution for the two-dimensional constraints in the at least one two-dimensional cluster; repeating the handling for any unprocessed two-dimensional clusters until all of the two-dimensional clusters are handled; and adopting the solution for each of the two-dimensional clusters to solve at least a portion of the plurality of constraints including the two-dimensional clusters. |
申请公布号 |
US8296706(B2) |
申请公布日期 |
2012.10.23 |
申请号 |
US20100767375 |
申请日期 |
2010.04.26 |
申请人 |
GRAY MICHAEL S.;TANG XIAOPING;YUAN XIN;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
GRAY MICHAEL S.;TANG XIAOPING;YUAN XIN |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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