发明名称 |
Low voltage differential signaling timing test system and method |
摘要 |
In a low voltage differential signal (LVDS) timing test system and method, a clock signal waveform and a data signal waveform are obtained. Clock cycles are selected from the clock signal waveform. Data bits transmitted within the selected clock cycles are identified from the data signal waveform. Accordingly, bit positions of the data bits are determined. |
申请公布号 |
US8290729(B2) |
申请公布日期 |
2012.10.16 |
申请号 |
US20100817149 |
申请日期 |
2010.06.16 |
申请人 |
HO JUI-HSIUNG;SU WANG-DING;HON HAI PRECISION INDUSTRY CO., LTD. |
发明人 |
HO JUI-HSIUNG;SU WANG-DING |
分类号 |
G01R29/027 |
主分类号 |
G01R29/027 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|