发明名称 POWER-ON-RESET CIRCUIT WITH LOW POWER CONSUMPTION
摘要 Methods, devices and circuits are provided for power-on-reset circuits with low static power consumption. One such circuit includes a detector that draws current from a supply voltage. The detector detects that the supply voltage has exceeded a trip-point voltage level and then disables current draw from the detector. The detector responds to an enable signal by enabling current draw from the detector. A pulse generator generates a reset signal in response the supply voltage transitioning from a voltage below the trip point voltage level to above the trip point voltage level. A monitor detects that the supply voltage has dropped and provides, in response thereto, the enable signal to the detector to enable current draw from the portion of the detector.
申请公布号 US2012256664(A1) 申请公布日期 2012.10.11
申请号 US201113082142 申请日期 2011.04.07
申请人 GUNTHER ANDRE;MAHOOTI KEVIN 发明人 GUNTHER ANDRE;MAHOOTI KEVIN
分类号 H03L7/00 主分类号 H03L7/00
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