| 摘要 |
<p>In this microprocessor (1), Y-bit signals for address selection of each of an instruction address signal (CA) and a data address signal (DA) are masked, and X-bit signals for bank selection of the instruction address signal (CA) and the data address signal (DA) are compared. As a result, if the signals do not match, the two addresses selected by the address signals (CA and DA) are accessed in parallel, whereas if the signals match, the selected two addresses are accessed in order, one at a time. Therefore, even if the number of banks or the bank capacity of shared memory (4) is modified, it is not necessary to newly design a conflict assessment circuit (9).</p> |
