发明名称 |
Method and apparatus of phase locking for reducing clock jitter due to charge leakage |
摘要 |
A phase lock loop is disclosed comprising a first phase detector configured to receive a first clock and a second clock and output a first detector output signal; a second phase detector configured to receive the first clock and the second clock and output a second detector output signal; a summing circuit to sum the first detector output signal and the second detector output signal into a control signal; a loop filter to filter the control signal into a refined control signal; and a controllable oscillator to generate the output clock in accordance with a control by the refined control signal. |
申请公布号 |
US8283984(B2) |
申请公布日期 |
2012.10.09 |
申请号 |
US20100830317 |
申请日期 |
2010.07.03 |
申请人 |
LIN CHIA-LIANG;REAL TEK SEMICONDUCTOR CORP. |
发明人 |
LIN CHIA-LIANG |
分类号 |
H03L7/00 |
主分类号 |
H03L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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