发明名称 RELIABLE SOLDER BUMP COUPLING WITHIN A CHIP SCALE PACKAGE
摘要 PURPOSE: A solder bump coupling within a chip scale package is provided to improve reliability by preventing the generation of cracks of a solder bump. CONSTITUTION: A semiconductor substrate(150) comprises one or more semiconductor devices. An UBM layer(140) is formed on the semiconductor device. A non-conductive layer(130) comprises a cross-section portion which defines a protrusion(132) at the top of a recess within the UBM layer. The protrusion is aligned along interface(142) between the UBM layer and the non-conductive layer. A solder bump(160) is coupled to the UBM layer through an opening(134) within the non-conductive layer. The solder bump comprises a part arranged between the protrusions.
申请公布号 KR20120110058(A) 申请公布日期 2012.10.09
申请号 KR20120031171 申请日期 2012.03.27
申请人 FAIRCHILD SEMICONDUCTOR CORPORATION 发明人 MATTHEW A. RING
分类号 H01L23/488 主分类号 H01L23/488
代理机构 代理人
主权项
地址