发明名称 |
FUNCTIONAL UNIT FOR VECTOR INTEGER MULTIPLY ADD INSTRUCTION |
摘要 |
<p>A vector functional unit implemented on a semiconductor chip to perform vector operations of dimension N is described. The vector functional unit includes N functional units. Each of the N functional units have logic circuitry to perform: a first integer multiply add instruction that presents highest ordered bits but not lowest ordered bits of a first integer multiply add calculation, and, a second integer multiply add instruction that presents lowest ordered bits but not highest ordered bits of a second integer multiply add calculation.</p> |
申请公布号 |
WO2012040545(A9) |
申请公布日期 |
2012.10.04 |
申请号 |
WO2011US52899 |
申请日期 |
2011.09.23 |
申请人 |
INTEL CORPORATION;WIEDEMEIER, JEFF;SAMUDRALA, SRIDHAR;GOLLIVER, ROGER |
发明人 |
WIEDEMEIER, JEFF;SAMUDRALA, SRIDHAR;GOLLIVER, ROGER |
分类号 |
G06F15/76;G06F7/00;G06F9/30 |
主分类号 |
G06F15/76 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|