| 摘要 |
There is a problem with a CMIS semiconductor integrated circuit using a High-k Gate insulation film that, in a device region having a short channel length and a narrow channel width, with an increase of the film thickness of an Interfacial Layer IL between the High-k Gate insulation film and a silicon-based substrate by activation annealing of source/drain regions, the absolute value of the threshold voltage increases. One of the inventions of the present application is a manufacturing method of a semiconductor integrated circuit device having a MISFET. The method includes the steps of covering the semiconductor substrate surface with an oxygen absorption film after forming a gate stack of the MISFET and a peripheral structure of the MISFET, performing annealing in that state to activate impurities in the source/drain, and subsequently removing the oxygen absorption film. |
