INTEGRATED CIRCUIT AND METHOD FOR REDUCING AN IMPACT OF ELECTRICAL STRESS IN AN INTEGRATED CIRCUIT

摘要

An integrated circuit (10) is connectable to a power supply (11) and comprises a plurality of modules on a common substrate, the plurality comprising at least one clock-gated module (12); and a controller unit (14) arranged to enable and disable provision of a clock signal (16) to the at least one clock-gated module; wherein the at least one clock-gated module comprises one or more electronic circuits (18, 20, 22) arranged to be, when the at least one clock-gated module is connected to the power supply and the provision is disabled (24), in a first state of an electrical stress condition during a first portion of a period of time and in a second state of less electrical stress than in the first state during a second portion of the period of time; and wherein the at least one clock-gated module is arranged to, when the at least one clock-gated module is connected to the power supply and the provision is disabled, switch the one or more electronic circuits between the first state and the second state such that a change of a characteristic of at least one of the one or more electronic circuits caused by the electrical stress condition is at least partially reduced.