发明名称 PWM SIGNAL GENERATING CIRCUIT AND PROCESSOR SYSTEM
摘要 <p>A PWM signal generating circuit comprises: a duty setting unit (10) that generates a duty control signal, which designates a duty ratio per period of a PWM signal, on the basis of an initial duty value, a target duty value, a clock signal and a slope setting signal that designates a slope setting value designating a slope at which the initial duty value reaches the target duty value; a period setting unit (20) that outputs a period setting value indicating the length of one period of the PWM signal; and an output control unit (30) that generates, on the basis of the clock signal, the PWM signal the period of which is in accordance with the period setting value and the duty ratio of which is in accordance with the value of the duty control signal. The duty setting unit (10) increases the initial duty value up to the target duty value each time the number of times, at each of which the number of clocks of the clock signal reaches the period setting value, reaches the slope setting value.</p>
申请公布号 WO2012132221(A1) 申请公布日期 2012.10.04
申请号 WO2012JP01287 申请日期 2012.02.24
申请人 RENESAS ELECTRONICS CORPORATION;FUJIWARA, YASUYUKI 发明人 FUJIWARA, YASUYUKI
分类号 H02M3/155 主分类号 H02M3/155
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