发明名称 Chip Stack Package
摘要 PURPOSE: A chip stacked type semiconductor package is provided to securely form laminate connection between chips by forming a male bump and a female bump on a bonding pad of an upper layer and a lower layer. CONSTITUTION: A male bump(12) is formed on a bonding pad of an upper chip(10). A female bump(22) is formed on a bonding pad of a lower chip(20). The male bump is inserted into the female bump. The male bump is composed of a conductive solder(16) and a copper filler(14) of a predetermined height. The copper filler is formed on the bonding pad of the upper layer by a primary plating process. The conductive solder is formed on the upper side of the copper filler by a secondary plating process. An underfill material is filled between the upper chip and the lower chip.
申请公布号 KR101185454(B1) 申请公布日期 2012.10.02
申请号 KR20100093123 申请日期 2010.09.27
申请人 发明人
分类号 H01L23/48;H01L21/60 主分类号 H01L23/48
代理机构 代理人
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