发明名称 |
Processor decoding extension instruction to store plural address extension information in extension register for plural subsequent instructions |
摘要 |
A processing unit has an extended register to which instruction extension information indicating an extension of an instruction can be set. An operation unit that, when instruction extension information is set to the extended register, executes a subsequent instruction following a first instruction for writing the instruction extension information into the extended register, extends the subsequent instruction based on the instruction extension information. |
申请公布号 |
US8281112(B2) |
申请公布日期 |
2012.10.02 |
申请号 |
US20080338245 |
申请日期 |
2008.12.18 |
申请人 |
YOSHIDA TOSHIO;HONDOU MIKIO;FUJITSU LIMITED |
发明人 |
YOSHIDA TOSHIO;HONDOU MIKIO |
分类号 |
G06F9/30 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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