发明名称 INTERFACE TO FULL AND REDUCE PIN JTAG DEVICES
摘要 The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.
申请公布号 US2012246530(A1) 申请公布日期 2012.09.27
申请号 US201213488956 申请日期 2012.06.05
申请人 WHETSEL LEE D.;TEXAS INSTRUMENTS INCORPORATED 发明人 WHETSEL LEE D.
分类号 G01R31/3177;G06F11/25 主分类号 G01R31/3177
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