发明名称 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILLED VIAS AND METHOD OF MANUFACTURE THEREOF
摘要 A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a via hole in the substrate, the via hole having a top end and a bottom end with the bottom end is larger than the top end; forming a pad on the substrate, the pad encloses the top end of the via hole; and reflowing a conductive filler having higher volume than the via hole over the via hole, the conductive filler having a protrusion extending from the bottom end and the bottom end entirely overlaps at least one surface of the protrusion.
申请公布号 US2012241973(A1) 申请公布日期 2012.09.27
申请号 US201113070789 申请日期 2011.03.24
申请人 CHUA LINDA PEI EE;DO BYUNG TAI;PAGAILA REZA ARGENTY 发明人 CHUA LINDA PEI EE;DO BYUNG TAI;PAGAILA REZA ARGENTY
分类号 H01L23/48;H01L21/44;H01L21/56 主分类号 H01L23/48
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