发明名称 NAND ARCHTECTURE INCLUDING RESITIVE MEMORY CELLS
摘要 A non-volatile memory device includes a first select transistor, a second select transistor, and a first string of first memory cells provided between the first and second select transistors. Each first memory cell has a first resistive memory cell and a first transistor. The first resistive memory cell is in series with a gate of the first transistor. The non-volatile memory device further includes a first bit line coupled to a drain of the first select transistor and a plurality of word lines. Each word line is coupled to one of the first memory cells.
申请公布号 US2012236650(A1) 申请公布日期 2012.09.20
申请号 US201113051296 申请日期 2011.03.18
申请人 NAZARIAN HAGOP;CROSSBAR, INC. 发明人 NAZARIAN HAGOP
分类号 G11C16/04;G11C11/00 主分类号 G11C16/04
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