| 摘要 |
Disclosed is a method and system for generic object detection using block-based feature computation and, more specifically, a method and system for massively parallel computation of object features sets according to an optimized clock-cycle matrix. The method uses an array of correlators to calculate block sums for each section of the image to be analyzed. A greedy heuristic scheduling algorithm is executed to produce an optimized clock cycle matrix such that overlapping features which use the same block sum do not attempt to access the block at the same time, thereby avoiding race memory conditions. The processing system can employ any of a variety of hardwired Very Large Scale Integration (VLSI) chips such as Field Programmable Gate Arrays (FPGAs), Digital Signal Processors (DSPs) and Application Specific Integrated Circuits (ASICs).
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