发明名称 Phase- locked loop
摘要 A phase-locked loop for generating an output signal including a signal generator arranged to generate an output, a comparison unit arranged to compare the output with a reference signal so as to provide a digital signal, and a loop filter arranged to generate a control signal for controlling the signal generator in dependence on the digital signal. The loop filter includes a proportional path having a digital filter arranged to generate a first component of the control signal for controlling the phase of the output generated by the signal generator, and an analogue integral path arranged to generate a second component of the control signal for controlling the frequency of the output generated by the signal generator.
申请公布号 GB201213601(D0) 申请公布日期 2012.09.12
申请号 GB20120013601 申请日期 2012.07.31
申请人 CAMBRIDGE SILICON RADIO LIMITED 发明人
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