| 摘要 |
A shaper of periodic sequence of packets of pulses with adjustable pulse width, number of pulses in a packet and a fixed pause between pulses equal to four cycles comprises two binary counters, first of which a reversible countdown counter has a clock input, a synchronous parallel load input and a loading data input, a counting mode enable input, an asynchronous reset, an overflow output, a second counter has a clock input, a counter mode enable input, an asynchronous reset, first and second OR elements, an inverter, a circuit comprising in series connected resistor and capacitor, a start/stop device comprising a synchronous D-flip-flop having an asynchronous reset, first and second OR elements. Third reversible countdown counter is introduced having a clock input, a synchronous parallel load input and a loading data input, a counting mode enable input, an asynchronous reset, an overflow output. |
