发明名称 |
PHASE LOCKED LOOP WITH CHARGE PUMP |
摘要 |
A phase locked loop (PLL) includes a voltage controlled oscillator (VCO) configured to supply an output signal. A phase frequency detector (PFD) is configured to receive a reference frequency signal and to provide a first control signal. A first charge pump is configured to receive the first control signal and to provide a first voltage signal in order to control the VCO. A second charge pump is configured to receive the first control signal and to provide a second voltage signal. A comparator is configured to receive a reference voltage signal, to compare the reference voltage signal and the second voltage signal, and to provide a second control signal. The PFD is configured to adjust at least one side slope of the first control signal based on the second control signal. |
申请公布号 |
US2012223752(A1) |
申请公布日期 |
2012.09.06 |
申请号 |
US201113039095 |
申请日期 |
2011.03.02 |
申请人 |
HUANG MING-CHIEH;LIN CHIH-CHANG;CHUNG TAO WEN;CHERN CHAN-HONG;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
HUANG MING-CHIEH;LIN CHIH-CHANG;CHUNG TAO WEN;CHERN CHAN-HONG |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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