发明名称 DELAY FAULT TESTING FOR CHIP I/O
摘要 An integrated circuit (IC) chip is provided. The IC chip includes a signal output via which an outgoing signal is transmitted, and a signal input via which an incoming data signal is received. Also included on the IC ship is a pass circuit to couple the signal output to the signal input during testing of the IC chip. Furthermore, a delay circuit produces a first timing signal and a second timing signal during testing of the IC chip. The second timing signal is delayed from the first timing signal according to a test parameter. The first timing signal triggers transmission of a test signal via the signal output, and the second timing signal triggers sampling of the received test signal via the signal input.
申请公布号 WO2012115840(A2) 申请公布日期 2012.08.30
申请号 WO2012US25311 申请日期 2012.02.15
申请人 RAMBUS INC.;FRANZON, PAUL, D. 发明人 FRANZON, PAUL, D.
分类号 G01R31/3183 主分类号 G01R31/3183
代理机构 代理人
主权项
地址