发明名称 METHOD OF OPTIMIZATION OF A MANUFACTURING PROCESS OF AN INTEGRATED CIRCUIT LAYOUT
摘要 A computer-implemented method, article of manufacture, and computer system for optimization of a manufacturing process of an integrated circuit or IC layout. The method includes: receiving input; organizing IC patterns; selecting IC patterns amongst the organized IC patterns; and optimizing a design of a manufacturing process of the IC layout based on the selected IC patterns.
申请公布号 US2012221984(A1) 申请公布日期 2012.08.30
申请号 US201213402941 申请日期 2012.02.23
申请人 INTERNATIONAL BUSINESS CORPORATION 发明人 DEMARIS DAVID L.;GABRANI MARIA;VOLKOVA EKATERINA
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址
您可能感兴趣的专利