| 摘要 |
A shaper of periodic sequence of packets with fixed pulse number in a packet, equal to three, with adjustable pulse width and pause between the packets comprises two binary countdown reversible counters, each of which has a clock input, a synchronous parallel load enable input and a loading data input, a counting mode enable input, an asynchronous reset, an overflow output, an inverter, first and second elements OR, a circuit comprising in series connected resistor and capacitor, a start-stop device comprising a synchronous D flip-flop having an asynchronous reset, first and second two-input elements AND. Third binary counter, third element OR, two AND-NOT element, a second inverter are introduced. The binary counter is designed using two J-K flop-flops, according a two-digit circuit having a scaling factor equal to three, it comprises a counting mode enable input, a first flip-flop has J input and two K inputs, I inputs of which are united, the second flop-flop has two J inputs, I inputs of which are united and the second input K. |
